1. Field of Invention
The present invention relates to the field of computers and computer processors, and more particularly to a method for parallel processing utilizing a combination of multiple computers on a single microchip, wherein operating efficiency is important because of the desire for increased operating speed. This invention relates to computer technology, particularly semiconductor microprocessor technology and with still greater particularity the arrangement of multiple processors on a single semiconductor to provide easier ability to connect and speed.
2. Description of the Background Art
Semiconductor technology advances by providing greater numbers of components in a given area of semiconductor. This has largely occurred due to advances in technology allowing the fabrication of ever smaller components. Smaller components also operate faster than larger components. The initial success of such operations has led to the construction of a microprocessor with associated RAM and ROM on a single chip. In recent years there have been first two microprocessors on a single chip, then four, and eight in the near future. As the number of processors increases, so also does the difficulty in the processors communicating with each other and the outside environment.
As the number of processors increases, the connections between the processors become a more difficult problem. The simplest method is to connect all processors to a common bus and allow the processors to communicate with each other through packet protocols. In two and four processor systems the processors are sometimes mirror images of each other for ease of connection. A difficulty with such an arrangement is that the advantage of multiple processors is rapidly lost through the complexity of the routing instructions. Each of the communications is received by each of the processors and ignored by those processors to which no communication is directed. As a result, system bandwidth rapidly deteriorates as the number of processors increases. There is thus a longstanding need for a method of arranging and connecting an unlimited number of processors without deterioration of system bandwidth.
Dividing a task and performing multiple processing and computing operations in parallel at the same time is known in the art, as are many systems and structures to accomplish this. An example is systolic array processing wherein a large information stream is divided up among rows of processors that perform sequential computations by column, and pass results to the next column. Other examples are found in the field of supercomputing, wherein multiple processors may be interconnected and tasks assigned to them in a number of different ways, and communication of intermediate results between processors and new data and instructions to them may be provided through crossbar switches, bus interconnection networks with or without routers, or direct interconnections between processors with message passing protocols such as MPICH, used on large machines.
Another solution has been to provide a switching network at the center of the processor array. The processors are all connected to this network, which allocates tasks and divides the work. The processors are not connected directly to each other and are sometimes mirror images of each other.